Monolithic ICs generally comprise a number of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), or more generally metal-insulating-semiconductor field-effect transistors (MISFETs), fabricated over a planar substrate, such as a silicon wafer. Current system on a chip (SoC) technologies are aggressively scaling the FET gate length (Lg) to provide performance and area scaling in accordance with Moore's Law.
One adverse effect of lateral scaling is that the support for low leakage and high voltage devices, both of which are important in SoC applications, becomes more difficult due to the architecture of high voltage transistors diverging from that of the minimum design-rule (nominal) logic transistor. Lateral scaling also reduces gate-contact spacing, which increases the peak electric field, further reducing a transistor's high voltage operating window.
Peak electric field along a length of a semiconductor channel region in a FET can be modulated through channel doping (e.g., high angle, low energy implantation, etc.). Depending on the gate electrode material, it may also be possible to modulate the field by engineering the gate electrode work function difference relative to the channel semiconductor by tuning the work function value of the gate electrode. For example, polysilicon gate electrodes may have impurities activated to different extents within the gate electrode. In other examples, a gate electrode may be split into two electrodes of different material that electrostatically couple through the gate dielectric to different portions of a channel region. Such structures however are not easily integrated with logic transistors operating at a relatively lower source/drain and/or gate/drain voltage, which do not share the sensitivity to peak electric field.
FET architectures and associated fabrication techniques that enhance high voltage operation of certain transistors without hindering low voltage logic transistor operation are advantageous, particularly for SoC technologies.